例句與造句

1. These commands set the interrupt masks, while returning their previous contents.
2. An interrupt status register and interrupt mask register were provided in each of the four processor states.
3. Processors typically have an internal " interrupt mask " which allows software to ignore all external hardware interrupts while it is set.
4. Setting or clearing this mask may be faster than accessing an interrupt mask register ( IMR ) in a PIC or disabling interrupts in the device itself.
5. There are three registers, an Interrupt Mask Register ( IMR ), an Interrupt Request Register ( IRR ), and an In-Service Register ( ISR ).
6. It's difficult to find interrupt mask in a sentence. 用interrupt mask造句挺難的
7. Later machines came out with interrupt masks, and BSD changed the names to more descriptive names such as splbio ( for block I / O ) and splhigh ( block out all interrupts ) ."
8. In addition, the SIM ( Set Interrupt Mask ) and RIM ( Read Interrupt Mask ) instructions, the only instructions of the 8085 that are not from the 8080 design, allow each of the three maskable RST interrupts to be individually masked.
9. In addition, the SIM ( Set Interrupt Mask ) and RIM ( Read Interrupt Mask ) instructions, the only instructions of the 8085 that are not from the 8080 design, allow each of the three maskable RST interrupts to be individually masked.
10. IBM devised a workaround ( implemented in the stack pointer and often the interrupt mask in the real-time clock chip's RAM . This allowed the BIOS to restore the CPU to a similar state and begin executing code before the reset.
11. SIM and RIM also allow the global interrupt mask state and the three independent RST interrupt mask states to be read, the pending-interrupt states of those same three interrupts to be read, the RST 7.5 trigger-latch flip-flop to be reset ( cancelling the pending interrupt without servicing it ), and serial data to be sent and received via the SOD and SID pins, respectively, all under program control and independently of each other.
12. SIM and RIM also allow the global interrupt mask state and the three independent RST interrupt mask states to be read, the pending-interrupt states of those same three interrupts to be read, the RST 7.5 trigger-latch flip-flop to be reset ( cancelling the pending interrupt without servicing it ), and serial data to be sent and received via the SOD and SID pins, respectively, all under program control and independently of each other.